Not Applicable.
Not Applicable.
The present embodiments relate to electronic circuits and are more particularly directed to designs for circuits including a number of metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistors and to optimize drive current capability versus area consumption and capacitance load.
Semiconductor devices have become prevalent in all aspects of electronic circuits, and the design of transistors used in such circuits typically takes into account various factors including layout area, power consumption, speed, and the like. Various computer-assisted design systems have arisen and many of these systems attempt to consider and optimize the above factors in developing circuit designs. These systems are able to increase the efficiency of circuit design, and the systems themselves are periodically improved which may therefore also improve the circuit designs resulting from the system. Indeed, the preferred embodiments discussed later form a basis to improve such systems as well as circuit design either by itself or as a result of such an improved computer-assisted design system.
By way of further background, FIG. 1 illustrates a plan view of a prior art transistor 10 in order to establish various terminology and related aspects to be used throughout this document. Transistor 10 is typically formed in connection with an underlying semiconductor substrate, although such a substrate is not visible from the plan perspective in FIG. 1. A semiconductor active region is defined relative to the substrate, such as by forming isolating regions 121, and 122, thereby defining the active region as the semiconductor area accessible at the upper semiconductor surface and between the isolating regions. Isolating regions 121 and 122 may be formed using shallow trench isolation (xe2x80x9cSTIxe2x80x9d) or other isolating techniques (e.g., field oxides), and while shown in FIG. 1 as separate regions they also may be a continuous region all around the perimeter of the active region. A gate G1 is formed, typically by patterning and etching a formed layer of polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) that is formed over the semiconductor substrate. In effect, gate G1 separates the active region into two areas generally to the sides of gate G1 and in which the source and drain of transistor 10 are formed. In many transistor configurations, the source and drain are physically alike and symmetric. Further, they also may be electrically connected so that for different instances current flow changes directions. Thus, for sake of general reference and unless specified otherwise, each such region is referred to as a source/drain in FIG. 1 and there is a source/drain S/D1 and a source/drain S/D2. Typically, source/drains S/D1 and S/D2 are formed by implanting dopants adjacent both edges of gate G1 and into the active region (where the active region may include one or more wells previously formed within the substrate). For example, for an n-type MOS transistor (xe2x80x9cNMOSxe2x80x9d), each source/drain S/D1 and S/D2 is formed by one or more implanting steps that implant n-type dopants, where these dopants are often self-aligned to gate G1 (and possibly to insulating sidewalls formed along gate G1, although such sidewalls are not shown to simplify the Figure and discussion). For each source/drain S/D1 and S/D2, a number of contacts are formed so that electrical access may be made to the respective source/drain. By way of reference and example in FIG. 1, these contacts are C1 through C4 with respect to source/drain S/D1, and these contacts are C5 through C8 with respect to source/drain S/D2. The techniques for forming contacts C1 through C8 may take various forms. Finally, note that gate G1 includes an electrical contact pad CP1 formed by extending the conductive gate material beyond the perimeter of the active region.
FIG. 1 further defines various dimensions which are noteworthy in prior art circuit design. First, in the dimension that gate G1 separates the active region into source/drains S/D1 and S/D2, and to the extent that gate G1 overlies the active region (i.e., as shown vertically in FIG. 1), is the width of gate G1, designated Wg. Note that gate G1 may extend beyond the active region such as shown in FIG. 1 in the vertical dimension, but the gate width Wg is defined only where the gate overlies the active region. Second, in the dimension that gate G1 is perpendicular to Wg is the length of gate G1, designated Lg. Often, Lg and Wg are established by a circuit designer, either manually or by a computer-assisted technique such as with a special design program used to develop transistor inclusive circuits. Moreover, as technology advances, the gate length Lg commonly decreases, and often there is a corresponding decrease in Wg. Indeed, in some contemporary circuits, a so-called set of design rules are established and which sets minimum limits to certain critical dimensions. Each transistor in the circuit is constructed such that these design rules are not violated by a dimension falling below any of the minimum limits. For example, under contemporary designs a typical set of design rules may dictate a minimum value of Lg=0.11 xcexcm and that for Wg=0.15 xcexcm.
FIG. 1 introduces two additional distances by way of further background to the preferred embodiment. Specifically, within each source/drain, each contact C1 through C8 is located in a position relative to gate G1 and relative to the outer perimeter, or edge, of the active region. The location of each such contact is also dictated by two distances, which are shown by way of example with respect to contact C2. Specifically, a distance CTE1 is shown as the contact-to-edge distance with respect to contact C2, that is, the distance between contact C2 and the edge of the active region. Additionally, a distance CTG1 is shown as the contact-to-gate distance with respect to contact C2, that is the distance between contact C2 and gate G1. Having illustrated these two distances, various observations may be made about them as relating to the typical implementation of the distances in the prior art. First, for a given source/drain (e.g., source/drain S/D1), the distances are the same for each contact. Thus, by way of example in FIG. 1, the same distances CTE1 and CTG1 apply to contacts C1 through C4. Second, in many configurations, the distances CTE1 and CTG1 apply to all contacts for both source/drains of the transistor. For example, under contemporary designs a typical set of design rule minimum values is CTE1=0.05 xcexcm and CTG1=0.095 xcexcm. Further, from these distances it is noted that FIG. 1 is not drawn to scale, but it is drawn in a manner to provide a relative basis for comparison to later Figures as will be appreciated below. Alternatively, for transistors not implementing the minimums in the design rules, they may implement a second set of distances with larger values for the contact-to-edge and contact-to-gate distances, along with corresponding larger values for Lg and Wg. Still further, note that often the limit for one critical dimension may be dependent on the value of another dimension. For example, the minimum from above of CTG1=0.095 xcexcm may apply where Lgxe2x89xa60.4 xcexcm while for Lg greater than 0.4 xcexcm then the minimum value for CTG1 may be CTG1=0.125 xcexcm. Generally, a transistor constructed according to the minimum dimensions allowed by the design rules consumes a lesser amount of integrated circuit area as compared to a transistor drawn using larger dimensions. Moreover, because minimizing area is often a key design goal, then typically most of the transistors in a circuit are constructed according to the minimum size allowed by the design rules, with the exception of Wg and Lg. The dimensions Wg and Lg for each transistor may be individually adjusted by the designer, either manually or with computer-assisted design systems to obtain a desired electrical behavior for a circuit.
While the preceding sets of rules and observations have proven useful in circuit design, the present inventors have observed various limitations and possible drawbacks to prior approaches. As the minimum dimensions allowed by the design rules have advanced and thereby dictated shorter distances, it has been observed that various operational limits may be imposed on certain transistors. As a particular example relevant to the preferred embodiments described later, it has been observed that as CTG is reduced to the minimum allowed by the design rules, the drive current in a p-type MOS transistor (xe2x80x9cPMOSxe2x80x9d) increases monotonically. However, it has been observed further than an NMOS transistor provides a lower amount of drive current as CTG is reduced below a certain value larger than the minimum allowed by the design rules. Thus, in connection with the preferred embodiments described below it is further observed in this case that there is an optimum value of CTG for which the drive current is maximized. Moreover, various hypotheses are suggested by the present inventors with respect to the cause(s) for this reduced drive current from the NMOS transistor, as described below.
As a first possible reason for the reduced drive current in an NMOS transistor implementing the minimums set by the design rules, those rules may impose significant stress on the NMOS transistor which therefore affects electron mobility. More particularly, the stress is believed to affect the effective mass in the valence and conduction bands of the crystalline structure and, indeed, more notably in the valence band. The effect reduces the electron mobility in the conduction band and, hence, reduces the drive current of an NMOS transistor constructed under the minimum CTG allowed by the design rules.
A second possible reason for the reduced drive current in an NMOS transistor under the minimum CTG distance allowed by the design rules relates to the formation of silicides over the source/drain regions of transistor 10. Particularly, while not shown in FIG. 1, it is known in the art that a low-resistance conductor is typically formed over each source/drain region so that electrical contact can be made to that conductor and, hence, to the underlying source/drain. Indeed, contacts C1 through C8 should be understood to contact these types of low resistance conductors. Often, the low-resistance conductor is a silicide formed over the underlying silicon portion of the source/drain. In this case, an interface exists between the silicide and the silicon source/drain, thereby presenting an electrical resistance along that interface. Given this interface resistance, it is known in the art that a so-called contact transfer length may be defined which defines a characteristic distance over which the current is transferred across the interface between the silicide and the silicon. To further address this aspect as well as the preferred embodiments described later, then the length of the silicided region that is perpendicular to the longer axis of the gate, and where this length is also therefore the length of the underlying active region in the same dimension, is hereafter referred to as Ls. Thus, given a particular transfer length, then a length of Ls that is substantially shorter than the contact transfer length may effectively cramp the flow of current. Consequently, when the design rules result in the use of a length of silicide region that is substantially smaller than the contact transfer length, then such an implementation also may affect (and limit) the amount of drive current in an NMOS transistor. Of course, by increasing Ls excessively a penalty is incurred in area with diminishing returns for lower series resistance.
Regardless of the actual cause of reduced NMOS drive current under the minimum design rules, the present inventors note that the result of limited current flow is ignored in the art and instead there is an indiscriminate use of the minimum dimensions in the design rules in an effort to reduce the area required by transistors on an integrated circuit. Such usage, therefore, may be perceived to increase device efficiency by reducing device size, but at the same time a cost, which may not be intentional, arises in that any NMOS transistors using the minimums set forth by the design rules may be underperforming in terms of current flow. As a result, such devices may slow the operation of the integrated circuit which may in some instances be very undesirable. In view of these observations, the preferred embodiments attempt to improve upon these attributes as appreciated from the remaining discussion below.
In one preferred embodiment, there is a method of designing a circuit comprising a plurality of transistors. Each transistor of the plurality of transistors comprises an active region, a gate, a first source/drain in the active region, a second source/drain in the active region, and at least one contact in each of the first source/drain and the second source/drain. The method comprises various steps. The method specifies a first set of distances for each transistor in a first set of transistors in the plurality of transistors, wherein the first set of distances comprises a gate length, a gate width, and a distance representative of one or both of a first contact-to-edge distance and a first contact-to-gate distance. The method also specifies a second set of distances for each transistor in a second set of transistors in the plurality of transistors, wherein the second set of distances comprises a gate length, a gate width, and a distance representative of one or both of a second contact-to-edge distance and a second contact-to-gate distance. For the method specifications, either or both the second contact-to-edge distance is greater than the first contact-to-edge distance and the second contact-to-gate distance is greater than the first contact-to-gate distance. Also for the method specifications, for each transistor in the second set of transistors, the step of specifying a second set of distances is responsive to a determination of a benefit from a larger drive current to be provided by the transistor in the second set of transistors. Other circuits, systems, and methods are also disclosed and/or claimed.